High-frequency circuits in BIPOLAR, BICMOS and CMOS technology require integrated capacitors with a high voltage linearity, accurately settable capacitances and in particular low parasitic capacitances. The conventional MOS or MIS capacitors which have been used hitherto have an unsatisfactory voltage linearity on account of voltage-induced space charge regions. The short distance from the substrate also entails numerous parasitic capacitances.
These difficulties can be avoided by using what are known as metal-insulator-metal capacitors (MIM capacitors), which are usually arranged between two metallization levels and are therefore at a considerably greater distance from the substrate. As far as possible, these metal-insulator-metal capacitors should be integrated in the existing concepts for multilayer metallization without changing and influencing the adjacent interconnects.
Previous approaches, such as for example those which are known from the printed specifications U.S. Pat. No. 5,946,567, EP 0 800 217 A1 and EP 1 130 654 A1 and the article “High Density Metal Insulator Metal Capacitors Using PECVD Nitride for Mixed Signal and RF Circuits”, IITC, pp. 245–247, IEEE (1999) by Kar-Roy et al. use the materials silicon dioxide and/or silicon nitride, which are well characterized and known in the micro-electronics industry, as dielectrics. However, the dielectric constants k of these materials are not especially high, at approximately four to seven. Furthermore, on account of the use in the multilayer metallization, they have to be deposited using plasma (PECVD) processes. These processes are typically distinguished by high deposition rates, but also by high defect densities and lower layer qualities. Therefore, in plasma processes it is virtually impossible to produce layers of less than 60 nm with a reproducible thickness and sufficient quality.
Moreover, in the integration concepts cited above, the top electrode is patterned with the aid of a top electrode etch, which has to be stopped in the dielectric of the capacitor. For this reason, these processes absolutely must have a dielectric layer with a sufficient thickness of at least 60 nm.
The starting point for the fabrication of an MIM capacitor according to the prior art is the stack shown in FIG. 4. In this case, an adhesive layer 2 of Ti, an interconnect 3 of Al and an antireflection coating (ARC) layer 5 of Ti/TiN are deposited onto a substrate 1. This stack has at the same time the function of a first electrode. A dielectric layer 6 is applied to this stack. Deposited above the dielectric layer 6 is the metal stack for the second electrode. It comprises two TiN (Ti) layers 8, 10 and an Al layer 9 lying in between. FIG. 5 shows a process stage in which the second electrode 8, 9, 10 and the dielectric 6 have already been patterned. As can be seen from the etching edge 16, the dielectric 6 in the region outside the second electrode 8, 9, 10 serves here as an etching stop.
The surface area-specific capacitance of known capacitors of this type is around 1 fF/μm2; however, for future high-frequency applications, a multiple of this capacitance will be required. The surface area-specific capacitance of a capacitor is substantially determined by the thickness of the dielectric separating layer and the dielectric constant. Therefore, the surface area-specific capacitance of a capacitor can be increased by using dielectrics with a high dielectric constant (>8). Furthermore, insulation layers which are thinner than 60 nm lead to an increase in the surface area-specific capacitance.
Working on the basis of the prior art described, the invention is based on the object of providing an improved integrated semiconductor product having interconnects and a metal-insulator-metal capacitor and of describing a method for its fabrication.